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TDA7333
RDS/RBDS PROCESSOR
1

Features
3rd ORDER HIGH RESOLUTION SIGMA DELTA CONVERTER FOR MPX SAMPLING DIGITAL DECIMATION AND FILTERING STAGES DEMODULATION OF EUROPEAN RADIO DATA SYSTEM (RDS) DEMODULATION OF USA RADIO BROADCAST DATA SYSTEM (RBDS) AUTOMATIC GROUP- AND BLOCK SYNCHRONIZATION WITH FLYWHEEL MECHANISM ERROR DETECTION AND CORRECTION PROGRAMMABLE INTERRUPT SOURCE (RDS BLOCK,TA) I2C/SPI BUS INTERFACE COMMON QUARTZ FREQUENCY 8.55 MHz or 8.664MHz
Figure 1. Package
TSSOP16
Table 1. Order Codes
Part Number TDA7333
Package TSSOP16

3.3V POWER SUPPLY, 0.35 m CMOS TECHNOLOGY
2
Description
The TDA7333 is a RDS/RDBS signal processor, intended for recovering the inaudible RDS/RBDS informations which are transmitted on most FM radio broadcasting stations.
Figure 2. Block Diagram
Cref REF1
4
Cref REF3
2
Cref
16pF
Cxti
16pF
Cxto XTO VDDA
1
REF2
3
XTI
9 10
VSS
5
VDDD
7
OSCILLATOR
MPX
16
Cmpx
SIGMA DELTA converter
SINC4 filter
BANDPASS filter
INTERPOLATOR
sinc4reg
MPX
SCL_CLK SDA_DATAIN SA_DATAOUT CSN
11 12 13 14
sdaout sdain sck spi testreg tm resetn
MPX
TEST LOGIC & PIN MUX's
I2C/SPI interface
RDS demodulator & synchronisation
INTN
15
INTN
6
8
TM
RESETN
January 2005
Rev. 1 1/21
TDA7333
3
Pin Connection
Figure 3. Pin Connection (Top view)
VDDA 1 REF3 2 REF2 3 REF1 4 VSS 5 TM 6 VDDD 7 RESETN 8 TDA7333
16 MPX 15 INTN 14 CSN 13 SA_DATAOUT 12 SDA_DATAIN 11 SCL_CLK 10 XTO 9 XTI
4
PIN DESCRIPTION
Table 2. Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name VDDA REF3 REF2 REF1 VSS TM VDDD RESETN XTI XTO SCL_CLK SDA_DATAIN SA_DATAOUT CSN INTN MPX Analog Supply Voltage Reference voltage 3 of A/D Converter (2.65V) Reference voltage 2 of A/D Converter (1.65V) Reference voltage 1 of A/D Converter (0.65V) Common Ground Testmode Selection (scan test) Digital Supply Voltage External Reset Input (active low) Oscillator Input Oscillator Output Clock Signal for I2C and SPI modes Data Line in I2C mode, Data Input in SPI mode Slave Address in I2C mode, Data output in SPI mode Chip Select (1=I2C mode, 0=SPI mode) Interrupt output (active low), prog. at buff.not empty,buff. full, block A,B,D ,TA, TA EON Multiplex Input Signal Function
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5
Quick Reference
Table 3. Quick Reference (Tamb = 25C, VDDA/VDDD = 3.3V, fosc = 8.55 MHz)
Symbol General VDDA/VDDD Tamb fosc Idd Pd SRDS VMPX fSPi fi2c Analog/Digital Power Supply Operating temperature Quartz Frequency Total Supply Current Power Dissipation RDS Input Sensitivity Input Range of MPX Signal Maximum Speed in SPI mode Maximum Speed in I2C mode 1 750 1 400 3.0 -40 8.55 or 8.664 10 33 3.3 3.6 +85 V C MHz mA mW mVrms mVrms MHz kHz Parameter Values Min. Typ. Max. Unit
6
6.1
Electrical Specifications
Absolute Maximum Ratings
Table 4. Absolute Maximum Ratings
Symbol VDD Vin Vout Vpeak Parameter 3.3 V Power Supply Voltages Input Voltage Output Voltage Maximum Peak Voltage 5V tolerant inputs 5V tolerant output buffers in tri-state Test Conditions Values Min. -0.5 -0.5 -0.5 Typ. Max. 4 5.5 5.5 6 Unit V V V V
6.2
General Interface Electrical Characteristics
Table 5. General Interface Electrical Characteristics
Symbol Iil Iih Ioz Parameter Low Level Input Current High Level Input Current Tri-state Output leakage Vi =0V Vi =VDD Vo =0V or VDD Vo =5.5V 1 Test Conditions Values Min. Typ. Max. 1 1 1 3 Unit A A A A
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6.3 Electrical Characteristics Tamb = -40 to +85 C, VDDA/VDDD = 3.0 to 3.6 V, fosc = 8.55 MHZ, unless otherwise specified VDDD and VDDA must not differ more than 0.15 V Table 6. Electrical Characteristics
Symbol Supply (pin 1,5,7) VDDD VDDA IDDD IDDA Pd Vil Vih Vilhyst Vihhyst Vhst Voh Vol Digital Supply Voltage Analog Supply Voltage Digital Supply Current Analog Supply Current Total Power Dissipation Low level input voltage High level input voltage Low level threshold input falling High level threshold input rising Schmitt trigger hysteresis High level output Voltage Low level output Voltage open drain, depends on external circuitry Iol =4mA, takes into account 200mV drop in the supply voltage 2.0 1.0 1.5 0.4 1.15 1.7 0.7 VDDD 0.4 3.0 3.0 3.3 3.3 2 8 33 0.8 3.6 3.6 V V mA mA mW V V V V V V V Parameter Test Conditions Values Min. Typ. Max. Unit
Digital Inputs( pin 6,8,11,12,13,14)
Digital Outputs (pin 12,13,15) are open drains
Analog Inputs (pin 16) VMPX SRDS RMPX fosc tsu gm Cxti,Cxto Fs OVR THD+N Input Range of MPX Signal RDS Detection Sensitivity Input Impedance of MPX pin Quartz Frequency Start up Time Transconductance Load Capacitance Sample Rate Oversampling Ratio Relative Total Harmonic Dist. plus Noise Decimated Sample Rate Attenuation at 57 kHz Attenuation Difference Bandpass Filter fs fp Sample Rate Passband Frequencies fosc =8.55 MHz 55.6 267.2 58.4 kHz kHz BW= 54.5 .. 59.5 kHz fosc =8.55 MHz f =57 kHz BW= 54.5 .. 59.5 kHz, unweigted, Vrds = 3mVrms fosc = 8.55 MHz 0.0006 16 4.275 38 27 dB 1 55k 8.55 or 8.664 10 0.75 Vrms mVrms Ohm MHz ms A/V pF MHz
Crystal parameters
Sigma Delta Modulator
Sinc4/16 Decimation Filter fs A57 267.2 -2.6 0.4 kHz dB dB
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Table 6. Electrical Characteristics (continued)
Symbol Rp fstop Rs Mi IC fI2C SPI fSPI tch tcl tcsu tcsh todv toh td tsu th clock frequency in SPI mode clock high time clock low time chip select setup time chip select hold output data valid output hold deselect time data setup time data hold time 0 1000 200 200 450 450 500 500 250 1 MHz ns ns ns ns ns ns ns ns ns clock frequency in I2C mode 400 kHz
2
Parameter Passband Ripple Stopband Corner Frequencies Stopband Attenuation Interpolation Factor
Test Conditions
Values Min. -0.5 53.0 -43 32 Typ. Max. +0.5 61
Unit dB kHz dB
7
Functional Description
7.1 Overview The new RDS/RBDS processor contains all RDS/RBDS relevant functions on a single chip. It recovers the inaudible RDS/RBDS information which are transmitted on most FM radio broadcasting stations. Due to an integrated 3rd order sigma delta converter, which samples the MPX signal, all further processing is done in the digital domain and therefore very economical. After filtering the highly oversampled output of the A/D converter, the RDS/RBDS demodulator extracts the RDS DataClock , RDS Data Signal and the Quality information. A next RDS/RBDS decoder will synchronize the bitwise RDS stream to a group and block wise information. This processing includes an error detection and error correction algorithm. In addition, an automatic flywheel control avoids exhaustive data exchange between the RDS/RBDS processor and the host. The device operates in accordance with the EBU (European Broadcasting Union) specifications. 7.2 Sigma Delta Converter The Sigma Delta Modulator is a 3rd order (second order-first order cascade) structure. Therefore a multibit output (2 bit streams) represents the analog input signal. A next digital noise canceller will take the 2 bit streams and calculates a combined stream which is then fed to the decimation filter. The modulator works at a sampling frequency of XTI/2. The oversampling factor in relation to the band of interest (57 kHz +- 2.4 kHz) is 38. 7.3 Sinc4/16 Decimation Filter The oversampled data delivered from the modulator are decimated by a value of 16 with a 4th order Sinc Filter. This is considered to be the optimum solution for high decimation factors and for a 3rd order sigma delta modulator.
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The architecture is a very economical implementation because digital multipliers are not required. It is implemented by cascading 4 integrators operating at full sampling rate (XTI/2) followed by 4 differentiators operating at the reduced sampling rate (XTI/2/16). Also wrap around logic is allowed and the internal overflow will not affect the output signal as long as a minimum required bit width is maintained. The transfer function of this Sinc4/16 filter is:
1 1 - z - M K H ( z ) = ---- -------------------- M 1 - z-1
with K = 4, M = 16 and its frequency response is:
M K sin -------- 2 1 j ) = ---- ----------------------- H(e M sin -- 2
with
f = 2 ---fs
Figure 4. Transfer function of a 4th order Sinc Filter, decimation factor is 16.
Sinc4/16 Transfer Function 0
10
20
30
Magnitude [dB]
40
50
60
70
80
90
100
0
0.2
0.4
0.6
0.8
1 1.2 Frequency [Hz]
1.4
1.6
1.8
2 x 10
6
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Figure 5. Magnitude Response of Sinc4/16 Filter in RDS Band
Sinc4/16 Transfer Function (RDS Band) 0
0.5
1
1.5
Magnitude [dB]
2
2.5
3
3.5
4
4.5
5
5.4
5.5
5.6
5.7 Frequency [Hz]
5.8
5.9 x 10
6
4
7.4 RDS Bandpass Filter and Interpolator The 8th order digital RDS bandpass filter is of type Tschebyscheff and centered at 57 kHz. With linear phase characteristics in the passband and approximately flat group delay it guarantees best filter function of the RDS and ARI signal. Four biquads are cascaded working at a common sampling frequency of XTI/2/16. Figure 6. Transfer Function of RDS Bandpass Filter
Transfer Function of RDS Filter 10 0 10 20 30
Magnitude [dB]
40 50 60 70 80 90 100
4
4.5
5
5.5 6 Frequency [Hz]
6.5
7 x 10
4
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Figure 7. Phase Response of the RDS Bandpass Filter
Phase of RDS Filter 3
2
1
Phase [Radians]
0
1
2
3 5.6 5.65 5.7 Frequency [Hz] 5.75 5.8 x 10
4
The output sample of the bandpass filter is picked up from a linear interpolator with sinc2 characteristics. The interpolation factor is 32. A zero cross detection is simply formed by taking the sign bit of the interpolated signal. This signal which contains only phase informations is processed by the RDS Demodulator. 7.5 Demodulator - The demodulator includes : - RDS quality indicator with selectable sensitivity - Selectable time constant of 57kHz PLL - Selectable time constant of bit PLL - time constant selection done automatically or by software Figure 8. Demodulator Block Diagram
MPX Input-stage (digital Filter)
Sine comp. Cosine comp.
ARI-indicator
57 kHz PLL
frequency offset comp.
mclk mclk
(8,550 or 8,664 MHz) to RDS group and block synchronisation module:
Clock Generator
RD RDSDAT RDSQUAL
from RDS group and block synchronisation module:
1187.5Hz PLL
RDS Data Extractor
Half Wave Integrator
Half Wave Extractor
RDS Quality Extractor
AR_RES
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The demodulator is fed by the 57 KHz bandpass filter and interpolated multiplex signal. The input signal passes a digital filter extracting the sinus and cosinus components, to be used for further processing. The sign of both channels are used as input for the ARI indicator and for the 57 KHz PLL. A fast ARI indicator determines the presence of an ARI carrier. If an ARI carrier is present, the 57 KHz PLL is operating as a normal PLL, else it is operating as a Costas loop. One part of the PLL is compensating the integral offset (frequency deviation between oscillator and input signal). One channel of the filter is fed into the half wave integrator. Two half waves are created, with a phase deviation of 90 degrees. One wave represents the RDS component, whereas the other wave represents the ARI component. The sign of both waves are used as reference for the bit PLL (1187.5 Hz). The RDS wave is then fed into the half wave extractor. This leads into an RDS signal, which after integration and differential decoding represents the RDS data. In a similar way a quality bit can be calculated. This is useful to optimize error correction. The module needs a fixed clock of 8.55 MHz. Optionally an 8.664 Mhz clock may be used by setting the corresponding bit in rds_bd_ctrl register (cf page 13). In order to optimize the error correction in the group and block synchronization module, the sensitivity level of the quality bit can be adjusted in three steps (cf page15). Only bits marked as bad by the quality bit are allowed to be corrected in the group and block synchronization module. Thus the error correction is directly influenced by this setup. The time constant of the 57KHz PLL and the 1187.5Hz PLL may be influenced by software (cf page13). This is useful in order to achieve a fast synchronization after a program resp. frequency change (fast time constant) and to get a maximum of noise immunity after synchronization (slow time constant). The user may choose between 2 possibilities via bit rds_bd_ctrl[1] (cf page13): a: Hardware selected time constant - In this case both pll time constants are reset to the fastest one with a reset from the group and block synchronization module. If the software decides to resynchronize, it generates a reset . Both PLL are set to the fastest time constant, which is automatically increased to the slowest one. This is done in four steps within a total time of 215.6ms (256 RDS clocks). b: Software selected time constant - In this case the time constant of both PLL can be selected individually by software.PLL time constants can be set independently.
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7.6 Group and block synchronization module The group and block synchronization module has the following features : - Hardware group and block synchronization - Hardware error detection - Hardware error correction using the quality bit information of the demodulator - Hardware synchronization flywheel - TAinformation extraction - reset by software (ar_res) Figure 9. Group and block synchronization block diagram
RDSCLK RDSDAT RDSQAL
from RDS Demodulator
Group & Block Synchronization Control Block next RDS bit
new Block available
rds_bd_h,rds_bd_l
read only RDSDAT(15:0) Syndrome register S(9:0) S(4:0) Correction logic Correct. pat.
rds_corrp
Block missed Q(3:0)
rds_qu
bit_int
rds_int
int set synch.
read only
read only
set read/write res
BLOCK D BLOCK A BLOCK B
TAEON
CP(9:5)
QU(0:3)
TA
AR_RES
Corrected Data_OK Syndrom zero
Quality bit counter ABH DBH BLOCKE detected
RDS block counter BLOCK A BLOCK B BLOCK D AR_RES TAEON TA
This module is used to acquire group and block synchronization of the received RDS data stream, which is provided in a modified shortened cyclic code. For the theory and implementation of the modified shortened cyclic code, please refer to the specification of the radio data system (RDS) EN50067. It further detects errors in the data stream. Depending on the quality bit information of the demodulator an error correction is made. The RDS data bytes are available to the software together with status bits giving an indication on the reliability of the data. It also extracts TA information which can be used as interrupt source (cf page 12).
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7.7 Programming through Serial bus interface The serial bus interface is used to access the different registers of the chip. It is able to handle both I2C and SPI transfer protocols, the selection between the two modes is done thanks to the pin CSN : - if the pin CSN is high, the interface operates as an I2C bus. - if the pin CSN is asserted low, the interface operates as a SPI bus. In both modes, the device is a slave, i.e the clock pin SCL_CLK is only an input for the chip. Depending on the transfer mode, external pins have alternate functions as following: Table 7.
pin SCL_CLK SDA_DATAIN SA_DATAOUT function in SPI mode (CSN=0) CLK (serial clock) DATAIN (data input) DATAOUT (data output) function in I2C mode (CSN=1) SCL (serial clock) SDA (data line) SA (slave address)
Eight registers are available with read or read/write access rights as following : Table 8.
register rds_int[7:0] rds_qu[7:0] rds_corrp[7:0] rds_bd_h[7:0] rds_bd_l[7:0] rds_bd_ctrl[7:0] sinc4reg[7:0] testreg[7:0] access rights read/write read read read read read/write read/write read/write function interrupt source setting,synch., bne information quality counter, actual block name error correction status, buffer ovf information high byte of current RDS block low byte of current RDS block frequency, quality sensitivity, plls setting sinc4 filter settings (for internal use only) test modes (for internal use only)
The meaning of each bit is described below :
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rd in s_ t re t v lue se a bit na e m a ss cce
bit 7 0 w rite r/w
bit 6 0
bit 5 0
bit 4 0
bit 3 0
bit 2 0
bit 1 0
bit 0 0 int r
bne ar_res synch itsrc2 itsrc1 itsrc0 r r/w r r/w r/w r/w
interrupt bit. It is set to one on every programmed interrupt. It is reset by reading rds_int register. interrupt source itsrc[2:0] select the interrupt source (1) synchronization information. 1: the module is already synchronized. 0: the module is synchronizing It is used to force a resynchronization. If it is set to one, the RDS modules are forced to resynchronization state. The bit is automatically reset. So it is always read as zero. RDS block. if 1, one block has been detected
(1) interrupt source nointerrupt R SB D lock blockA blockB blockD T A T EN AO itsrc2 0 0 0 1 1 1 1 itsrc1 0 0 1 0 0 1 1 itsrc0 0 1 1 0 1 0 1
rds_int and rds_bd_ctrl write order (when in SPI mode) 1: rds_int and rds_bd_ctrl are updated with data shifted in. 0: rds_int and rds_bd_ctrl are not updated.
Note : when changing the interrupt mode, one has to perform a reset of the module (i.e set the bit "ar_res" at one)
rds_qu reset value bit name access
bit 7 0 qu3 r
bit 6 0 qu2 r
bit 5 0 qu1 r
bit 4 0 qu0 r
bit 3 0 blk1 r
bit 2 0 blk0 r
bit 1 0 e r
bit 0 0 synz r
It indicates if the error correction was successfull. 1: the syndrome was zero after the error correction. 0: the syndrome did not become zero and therefore the correction was not successfull. 1: a block E is detected.This indicates a paging block which is defined in the RBDS specification used in the united states of America. 0: an ordinary RDS block A, B, C, cor D is detected, or no valid syndrome was found. bit 0 of block counter (2) bit 1 of block counter (2) bit 0 of quality counter (3) bit 1 of quality counter (3) bit 2 of quality counter (3)
(2) block name block A block B block C,C' block D blk1 0 0 1 1 blk0 0 1 0 1
bit 3 of quality counter (3)
(3) qu[3..0] is a counter of the quality bit information coming from the RDS demodulator. It is counting the number of bits which are marked as bad by the demodulator. Only those bits are allowed to be corrected. Thus the quality bit counter indicates the maximum possible number of bits being corrected.
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rd rrp s_co re t va se lue bit na e m a ss cce
bit 7 0 cp9 r
bit 6 0 cp8 r
bit 5 0
bit 4 0
bit 3 0
bit 2 0
bit 1 0
bit 0 0 r
cp7 cp6 r r
cp5 correct dat_ok r r r
It is an information about a correct syndrome after reception resp. after an error correction routine. 1: a correct syndrome was detected. 0: the syndrome was wrong. The current RDS data cannot be used. It is an information about error correction. 1: an error correction was made. 0: the actual RDS block is detected as error free. bit 5 of the syndrome register(*) bit 6 of the syndrome register(*) bit 7 of the syndrome register(*) bit 8 of the syndrome register(*) bit 9 of the syndrome register(*) (*) (refer to: Specification of the radio data system EN50067 of CENELEC, ANNEX B). When bits 4...0 of the syndrome register are all zero a possible error burst is stored in this bits. With the help of the correction pattern(bits 9..5 of the syndrome register), the type of error can be measured in order to classify the reliability of the correction.
rds_bd_h reset value bit name access
bit 7 0 m15 r
bit 6 0 m14 r
bit 5 0
bit 4 0
bit 3 0 m11 r
bit 2 0 m10 r
bit 1 0 m9 r
bit 0 0 m8 r
m13 m12 r r
bit 15 of the actual RDS 16bits information bit 14 of the actual RDS 16bits information bit 13 of the actual RDS 16bits information bit 12 of the actual RDS 16bits information bit 11 of the actual RDS 16bits information bit 10 of the actual RDS 16bits information bit 9 of the actual RDS 16bits information bit 8 of the actual RDS 16bits information
rds_bd_l reset value bit name access
bit 7 0 m7 r
bit 6 0 m6 r
bit 5 0 m5 r
bit 4 0 m4 r
bit 3 0 m3 r
bit 2 0 m2 r
bit 1 0 m1 r
bit 0 0 m0 r
bit 7 of the actual RDS 16bits information bit 6 of the actual RDS 16bits information bit 5 of the actual RDS 16bits information bit 4 of the actual RDS 16bits information bit 3 of the actual RDS 16bits information bit 2 of the actual RDS 16bits information bit 1of the actual RDS 16bits information bit 0 of the actual RDS 16bits information
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rds_bd_ctrl re t va se lue bit nam e a ss cce
bit 7 0
bit 6 0
bit 5 0
bit 4 0
bit 3 0
bit 2 0 pllf r/w
bit 1 0 shw r/w
bit 0 1 r
freq qsens1 qsens0 pllb1 pllb0 r/w r/w r/w r/w r/w
select PLL's time constants by software or hardware: 1: software. Time constants are selected by pllb[1:0] resp. pllf 0: hardware. (reset value) Time constants automatically increase after a reset. set the 57kHz pll time constant (1) bit 0 of 1187.5Hz pll time constant (2) bit 1 of 1187.5Hz pll time constant (2) bit 0 of quality sensitivity (3) bit 1 of quality sensitivity (3)
(1) pllf 0 1 lock tim neededfor 90degdeviation e 2m s 10m s
select oscillator frequency: 1: 8.664MHz 0: 8.55MHz (reset value)
(2) pllb1 0 0 1 1 pllb0 0 1 0 1 lock tim neededfor 90degdeviation e 5m (reset status) s 15m s 35m s 76m s
(3) select sensitivity of quality bit. 00: minimum (reset value) 11: maximum
Note : Sinc4reg and testreg are reserved registers dedicated to testing and evaluation.
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8
I2C Transfer Mode
This interface consists of three lines: a serial data line (SDA), a bit clock (SCL), and a slave address select (SA). The interface is capable of operating in fast mode (up to 400kbits/s) but also at lower rates (<100kbits/s). Data transfers follow the format shown in Fig.8 . After the START condition (S), a slave address is sent. The address is 7 bits long followed by an eighth bit which is a data direction bit (R/_W). A 'zero' indicates a transmission (WRITE), a 'one' indicates a request for data (READ). The slave address of the chip is set to 001000S, where S is the least significant bit of the slave address set externally via the pin SA_DATAOUT. This allows to choose between two addresses in case of conflict with another device of the radio set. Each byte has to be followed by an acknowledge bit (SDA low). Data is transfered with the most significant (MSB) bit first. A data transfer is always terminated by a stop condition (P) generated by the master. Figure 10. I2C data transfer
SDA
SCL S
START CONDITION
1-7
ADDRESS
8
R/W
9
ACK
1-7
DATA
8
9
ACK
1-7
DATA
8
9
ACK/ACK
P
STOP CONDITION
8.1 Write transfer Figure 11. I2C write transfer
S
S lave address
W
A
rds_int
A
r d s_ b d _c trl
A
sinc4reg
A
testreg
A
P
from master to slave from slave to master
S = start condition W = write mode Slave address = 001000S ( where S is the level of the pin SA_DATAOUT) A = acknowledge bit P = stop condition
Figure 12. I2C write operation example : write of rds_int and rds_bd_ctrl registers
SA
0
CSN 1
SDA
rds_int[7:0]
rds_bd_ctrl[7:0]
SCL S SLAVE ADDRESS START CONDITION W ACK ACK ACK P STOP CONDITION
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8.2 Read transfer Figure 13. I2C read transfer
S
S lave addre ss
R
A
rds_int
A
rd s_qu
A
testreg
A
P
from master to slave from slave to master
S = start condition R = read mode Slave address = 001000S ( where S is the level of the pin SA_DATAOUT) A = acknowledge bit P = stop condition
Eight bytes can be read at a time (please refer to the to the pages ??? to ??? for the meaning of each bit). The master has always the possibility to read less than eight registers by not sending the acknowledge bit and then generating a stop condition after having read the needed amount of registers. There are two typical read access : - read only the first register rds_int to check the interrupt bit. - read the first five registers rds_int, rds_qu, rds_corrp, rds_bd_h, rds_bd_l to get the RDS data The registers are read in the following order : rds_int, rds_qu, rds_corrp, rds_bd_h,rds_bd_l, rds_bd_ctrl, sinc4reg, testreg. Figure 14. I2C read access example 1: read of 5 bytes
SA
0
CSN1
SDA
rds_int[7:0]
rds_qu[7:0]
rds_corrp[7:0]
rds_bd_h[7:0]
rds_bd_l[7:0]
SCL S SLAVE ADDRESS START CONDITION R ACK ACK ACK ACK ACK ACK STOP CONDITION P
Figure 15. I2C read access example 2: read of 1 byte
SA
0
CSN 1
SDA
rds_int[7:0]
SCL S SLAVE ADDRESS START CONDITION R ACK ACK P STOP CONDITION
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8.3 SPI mode Figure 16. SPI data transfer
CSN
tcsu
1
tsu
2
th
3 4
todv toh
5
tcl tch
6 7 8 63 64
tcsh
td
CLK
DATAIN DATAOUT
rds_int[7] rds_int[6] rds_int[5] rds_int[4] rds_int[3] rds_int[2] rds_int[1] rds_int[0]
rds_int[1] rds_int[0]
testreg[1] testreg[0]
update of shiftregister with registers content
shift of DATAIN in shiftregister
update of registers with shiftregister content if requested
This interface consists of four lines. A serial data input (DATAIN), a serial data output (DATAOUT), a chip select input (CSN) and a bit clock input (CLK). The chip select input signals the begin and end of the data transfer. If the data transfer starts, at each bit clock one bit is clocked out via the serial data output and one bit is clocked in via the serial data input. When chip enable signals the begin of the data transfer the internal 64 bits shift register is updated with the current registers content of the V324. When chip enable signals the end of the data transfer the registers with write access can be updated with the bits which have been last shifted in. The last byte on DATAIN input is always rds_int[7:0] and the former last one is rds_bd_ctrl[7:0]. In other words, the master has to take in account the amount of bytes transmitted when intending to perform a write operation so that the last two bytes sent on DATAIN are rds_bd_ctrl[7:0] and rds_int[7:0]. If the update of both rds_int and rds_bd_ctrl registers is actually taking place depends on the MSB of rds_int, i.e. rds_int[7] = 0 - no update, rds_int[7] = 1 update of both registers. Hereafter you can find typical read/write access in spi mode : Figure 17. write rds_int and rds_bd_ctrl registers in spi mode,reading RDS data and related flags
CSN
CLK
rds_bd_ctrl[7:0] {1,rds_int[6:0]}
DATAIN DATAOUT
rds_int[7:0] rds_qu[7:0] rds_corrp[7:0]
rds_bd_h[7:0]
rds_bd_l[7:0]
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Figure 18. read out RDS data and related flags, no update of rds_int and rds_bd_ctrl registers
CSN
CLK
{0,x,x,x,x,x,x,x}
DATAIN DATAOUT
rds_int[7:0] rds_qu[7:0] rds_corrp[7:0] rds_bd_h[7:0]
rds_bd_l[7:0]
Figure 19. write rds_int registers in spi mode,reading 1 register
CSN
CLK
{1,rds_int[6:0]}
DATAIN DATAOUT
rds_int[7:0]
The content of the rds registers is clocked out on DATAOUT pin in the following order: rds_int[7:0], rds_qu[7:0], rds_corrp[7:0], rds_bd_l[7:0], rds_bd_h[7:0], rds_ctrl[7:0], sinc4reg[7:0], testreg[7:0] For the meaning of the single bits please refer to the pages 13 to 15 . Note : After 40 bit clocks the whole RDS data and flags are clocked out.
9
Application Notes
A typical rds data transfer could work like this: 1. The micro sets the interrupt source to "RDS block" interrupt by setting itsrc[2:0] to 001. 2. The micro continuously checks the rds_int[7:0] bits for the first interrupt ( rds_int[0] goes high). If there is no interrupt it stops the transfer after these 8 bits. No update of the rds_int[7:0] is performed. 3. Once there is an interrupt detected the micro will also clock out all the other RDS bits (rds_qu[7:0], rds_corrp[7:0], rds_bd_h[7:0], rds_bd_l[7:0]). 4. The next interrupt can not be expected before 22ms. The above example is working by polling the rds_int[0] bit. An easier and better application is possible by checking the RDS interrupt pin INTN ( see below ) and starting the transfer only when this interrupt is present. The output pin INTN acts as an interrupt pin. The source of interrupt is programmable through the register rds_int ( cf page 11), the value on the pin is the inverted value of the bit rds_int[0] ( i.e this interrupt pin is active low). With the help of this pin an interrupt driven request of the rds data is possible (The external processor only starts the transfer if an interrupt is active).
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10 Package Information
Figure 20. TSSOP16 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 b c D (1) E 0.050 0.800 0.190 0.090 4.900 6.200 5.000 6.400 4.400 0.650 0.450 0.600 1.000 0 (min.) 8 (max.) 0.100 0.004 0.750 0.018 1.000 TYP. MAX. 1.200 0.150 1.050 0.300 0.200 5.100 6.600 4.500 0.002 0.031 0.007 0.005 0.114 0.244 0.170 0.118 0.252 0.173 0.026 0.024 0.039 0.030 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.009 0.122 0.260 0.177 inch
OUTLINE AND MECHANICAL DATA
E1 (1) 4.300 e L L1 k aaa
Note: 1. D and E1 does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side.
TSSOP16 (Body 4.4mm)
0080338 (Jedec MO-153-AB)
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11 Revision History
Table 9. Revision History
Date January 2005 Revision 1 First Issue Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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